Research & Publications

We show the effect of Ga-doping on the electrical and optical properties of thermally evaporated ZnO films.

The article deals with the modeling of gate voltage controlled resonant tunneling transport in a complementary-metal–oxide–semiconductor (CMOS) compatible double quantum dot channel nanowire field-effect-transistor (FET). Appropriate applied voltages at two separate gates, gate-1 and gate-2 of the device form two voltage-tunable quantum dots underneath the gates, within the nanowire channel. The quantum dot eigenstates are tuned by varying the applied gate voltages to enable voltage-modulated resonant tunneling transport. Such transport is modeled by employing a Schrödinger-Poisson self-consistent framework using non-equilibrium Green’s function (NEGF) formalism. Electron–phonon scattering within the nanowire channel is also considered. The transfer characteristics exhibit multiple current thresholds in the range of 10^(−4) uA/um – 1 uA/um due to resonant tunneling. The phonon scattering is observed to significantly depend on nanowire geometry and applied gate voltages, with tunneling dominated quasi-ballistic transport occurring at higher gate voltages. Also, steep sub-threshold slopes of 30 mV/decade–8 mV/decade range and transconductance in the range of 10^(−7) uS/um – 1 uS/um at room temperature are obtained by varying the nanowire diameter in the range of 20 nm – 5 nm. Therefore, such device architecture exhibits significant potential for achieving multi-current thresholds in a CMOS compatible architecture at room temperature.

This work investigates the material-dependent charge qubit performance of a gate voltage-induced double-quantum-dot gate nanowire channel field-effect transistor (DQD-NWFET) device through charge stability, Bloch sphere coverage, anti-crossing energy, and dephasing time. In this device, voltages at two localized gates along the nanowire channel create two quantum dots in series, which are further tuned by these voltages for the relevant qubit operations. To understand the material-dependent performance of the device, a self-consistent Schrodinger-Poisson framework coupled to non-equilibrium Green’s function formalism is developed. The study indicates that the charge qubit performance of the device significantly depends on the transport effective mass, with slight dependence on nanowire permittivity. It is observed that the increase in transport effective mass leads to sharpening of the “hyperbolic” nature of the charge stability diagram, along with a significant reduction in anti-crossing energy and Bloch sphere coverage. Consequently, anti-crossing energy in the range of 3–25 meV and dephasing time in the range of 25–130 ns can be achieved by varying the transport effective mass and nanowire permittivity from 0.04 to 0.10 and 10–16, respectively. The performance of the device is further studied for specific nanowire materials by taking into account the appropriate material parameters. Therefore, this study enables material engineering of nanowire FET devices for realizing superior charge qubit performance.

In this work, a Si/SiO2/Ge/SiO2/Pt resonant tunneling device (RTD) with an asymmetric double barrier has been modeled by adopting NEGF formalism. The impact of Ge-quantum well widths below, equal and above its ex-citonic Bohr radius (EBR ~25 nm) on resonant tunneling current is investigated at room temperature. The tunneling current peaks are observed to appear for decreasing the well width to equal or less than the EBR of Ge. Such peak values increase with downscaling of the well width up to a certain value and then it decreases with further miniaturization. The maximum peak current is obtained to be ~13 mA/cm^2 for Ge-well width of 17 nm. The corresponding maximum peak-to-valley current ratio (PVCR) is estimated to be ~18 at room temperature, which is larger in order than the conventional RTDs. Therefore, the current work may provide the route for fabrication of Si/Ge based high performance resonant tunneling devices operational at room temperature.

The current work explores a geometrically engineered dual-gate GaAs nanowire FET with stateof-the-art miniaturized dimensions (of nanowire diameter and gate seperation) for high performance charge qubit operation at room temperature. Relevant gate voltages in such device can create two voltage-tunable quantum dots (VTQDs) underneath the gates, as well as can manipulate their eigenstate detuning and the inter-dot coupling to generate superposition, whereas a small drain bias may cause its collapse leading to qubit read-out. Such qubit operations, i.e., ‘Initialization’, ‘Manipulation’, and ‘Measurement’, are theoretically modeled in the present work by developing a second quantization filed operator based Schrodinger-Poisson self-consistent framework coupled to non-equilibrium Green’s function (NEGF) formalism. The study shows that the Bloch sphere coverage can be discretized along polar and azimuthal directions by reducing the nanowire diameter and increasing the inter-dot separation respectively, that can be utilized for selective information encoding. The theoretically obtained stability diagrams suggest that downscaled nanowire diameter and increased gate separation sharpen the ‘bonding’ and ‘anti-bonding’ states with reduced anticrossing leading to a gradual transformation of the ‘hyperbolic’ current mapping into a pair of ‘straight lines’. However, the dephasing time in the proposed GaAs VTQD-based qubit may be significantly improved (~10 ns to ~100 ns) by scaling down both the nanowire diameter and gate separation to ~5-3 nm. Therefore, the present study suggests an optimization window for geometrical engineering of a dual-gate nanowire FET qubit to achieve a selective coverage of Bloch sphere for particular information encoding, stability diagram of desired resolution with minimum anticrossing, and an extensively improved dephasing time. Most importantly, such device is compatible with the mainstream CMOS technology and can be utilized for large scale implementation by little modification of the state-of-the-art fabrication processes.